We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 14425

Virtex-II/-II Pro/-4/-5 FPGA DCM - Resetting after configuration is strongly recommended for a DCM that is configured with external or internal feedback (VHDL/Verilog)


If a DCM is configured with internal or external feedback, applying a reset after configuration is strongly recommended for both production and ES devices to ensure consistent locking. This applies to Virtex-II, Virtex-II Pro, Virtex-4, and Virtex-5 devices.

Following are the reasons for this recommendation and example VHDL/Verilog code:


External Feedback Configuration

For an optimum locking process, a DCM with feedback configuration requires both CLKIN and CLKFB to be present and stable when the DCM begins to lock. It is not possible to provide CLKFB in the beginning of the locking process during configuration with external feedback. At the end of configuration, the DCM will begin to lock once the device enters the startup sequence. Because GTS is still asserted during this time, the output I/O pins are still in a 3-state condition, effectively putting the CLKFB signal into a 3-state condition.

When CLKFB eventually appears (after GTS is de-asserted), the DCM will proceed with the lock. However, it might not lock at the optimal point and could introduce slightly more jitter (as well as greater clock cycle latency) through the DCM.

In addition, if CLKFB is coupling with another signal when it is put into a 3-state condition (a PCB signal integrity issue), DCM might sense this invalid clock as CLKFB and use it to proceed with a lock. This second possibility might cause the DCM to not lock properly once GTS de-asserts and the true CLKFB signal is present. Use of reset after configuration guarantees that the locking process starts with a valid CLKIN and CLKFB signal and ensures consistent locking.

Internal Feedback Configuration

If the input clock oscillator cannot be guaranteed to be stable during configuration, and the feedback is internal, reset should be applied after configuration to ensure that proper locking occurs.


- If you alter the startup sequence (e.g., using the BitGen option), do not place the "LCK_cycle" (wait for DCM to lock) before the "GTS_cycle" (de-assert GTS); otherwise, the DCM will never lock and configuration will not complete.
- The default value is "-g LCK_cycle:NoWait" and "-g GTS_cycle:5". When these settings are used, the startup sequence is not held to wait for DCM to lock.
- For external feedback, the GTS_cycle must be set before the GWE_cycle in the BitGen options (this is the default). This ensures that DCM is reset after the I/O pins are activated.
- If you are using the Virtex-4 device, please ensure you meet the 200 ms reset requirement. See (Xilinx Answer 21127).

Verilog example:

// DCM instantiation to show the reset connection
DCM u_dcm1 (.CLKIN(clkin),

// rstin connects to RST pin of DCM
assign rstin = (user_reset || config_rst);

// This is the actual reset circuit that outputs config_rst. It is a four-cycle shift register.
FDS flop1 (.D(1'b0), .C(clkin), .Q(out1), .S(1'b0));
FD flop2 (.D(out1), .C(clkin), .Q(out2));
FD flop3 (.D(out2), .C(clkin), .Q(out3));
FD flop4 (.D(out3), .C(clkin), .Q(out4));

//config_rst will be asserted for 3 clock cycles.
assign config_rst = (out2 | out3 | out4);

VHDL example:

-- DCM instantiation to show the reset connection
u_dcm1: DCM port map (
CLKIN => clkin,
CLKFB => clkfb,
CLK0 => clk0,
RST => rstin,
LOCKED => locked);

-- rstin connects to RST pin of DCM
rstin <= user_reset or config_rst;

-- This is the actual reset circuit that outputs config_rst. It is a four-cycle shift register.
flop1: FDS port map (D => '0', C => clkin, Q => out1, S => '0');
flop2: FD port map (D => out1, C => clkin, Q => out2);
flop3: FD port map (D => out2, C => clkin, Q => out3);
flop4: FD port map (D => out3, C => clkin, Q => out4);

-- config_rst will be asserted for 3 clock cycles.
config_rst <= out2 or out3 or out4;

Linked Answer Records

Associated Answer Records

AR# 14425
Date 12/15/2012
Status Active
Type General Article
  • Virtex-II
  • Virtex-II Pro
  • Virtex-II Pro X
  • More
  • Virtex-II QPro/R
  • Virtex-5QV
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5Q
  • Virtex-4 QPro/R
  • Virtex-4 SX
  • Virtex-4 FX
  • Virtex-4 LX
  • Less
  • Digital Clock Manager (DCM) Module