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AR# 14430

XST - "ERROR:HDLParsers:812 - file_name.vhd Line xx. A value is missing in case."

Description

General Description:

When I construct case statements in VHDL, the following error occurs:

"ERROR:HDLParsers:812 - file_name.vhd Line 21. A value is missing in case."

This error message appears when VHDL code similar to the following is used:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity case_test is

Port (a : in std_logic_vector(3 downto 0);

b : in std_logic_vector(3 downto 0);

c : in std_logic_vector(3 downto 0);

d : in std_logic_vector(3 downto 0);

sel : in std_logic_vector (1 downto 0);

res : out std_logic_vector(3 downto 0));

end case_test;

architecture case_test_arch of case_test is

begin

process (sel, a, b, c, d) is begin

case (sel) is

when "00" => res <= a;

when "01" => res <= b;

when "10" => res <= c;

when "11" => res <= d;

end case;

end process;

end case_test_arch;

Solution

It appears that all cases have been specified; however, because the type "std_logic_vector" is being used, data types other than "1" or "0" must be included to fully specify the case statement. Although the example above uses the "std_logic_vector" type, the error message can occur with any data type in VHDL.

If you do not wish to specify all other data types, you can avoid the error by adding the following line:

when others => res <= a;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity case_test is

Port (a : in std_logic_vector(3 downto 0);

b : in std_logic_vector(3 downto 0);

c : in std_logic_vector(3 downto 0);

d : in std_logic_vector(3 downto 0);

sel : in std_logic_vector (1 downto 0);

res : out std_logic_vector(3 downto 0));

end case_test;

architecture case_test_arch of case_test is

begin

process (sel, a, b, c, d) is begin

case (sel) is

when "00" => res <= a;

when "01" => res <= b;

when "10" => res <= c;

when "11" => res <= d;

when others => res <= a; -- Default statement added

end case;

end process;

end case_test_arch;

However, if the case statements are not fully specified in your design, you must ensure that all of your cases are resolved according to design specifications.

AR# 14430
Date Created 08/29/2007
Last Updated 12/15/2012
Status Active
Type General Article