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AR# 14444

XC18V00/XC1700/XCFxx - PROM frozen after the power cycling test; configuration fails after power-on reset/initial power up. What are the requirements for power cycling XC1700/XC18V00/XCFxx PROM?


General Description:

What are the requirements for power cycling XC1700/XC18V00/XCFxx PROM?


For information related to the Resolution below, please see the following data sheets at:


"Platform Flash In-System Programmable Configuration PROMs"

"XC18V00 Series In-System Programmable Configuration PROMs"

"XC17V00 Series Configuration PROMs"

"XC1700E and XC1700L Series Configuration PROMs"

"Spartan-II/IIE Family of One-Time Programmable Configuration PROMs (XC17S00A)"

"Spartan Family of One-Time Programmable Configuration PROMs (XC17S00)"

At power up, the device requires the VCC power supply to monotonically rise from 0 V to nominal voltage within the specified VCC rise time (between 1ms~50ms for 1700; between 0.2ms~50ms for 18V00 and XCFxxS/P PROMs). If the power supply cannot meet this requirement, the device might not perform power-on-reset properly.

Performing power-on-reset, the PROM VCCINT must reach 0 V. If the board is powered back up before the VCCINT reaches 0 V, the PROM might fail to function correctly.

Because the 1700E/L, 17S00/XL/A, 17V00, PROMs have a lower POR threshold, they are more susceptible to power cycle issues. 18V00 and XCFxx PROMs have a higher POR threshold as well as improved POR circuits, and consequently, they are not as susceptible to power cycle issues. Therefore, it is critical to meet the power-on-reset requirement for the 1700 PROMs. However, Xilinx strongly recommends that system designs should bring VCC back down to 0 V when power cycling.

Is there any danger of corrupting the XC18V00 PROM contents through power fluctuations?

There is no explicit write protection mechanism in the XC18V00 that prevents attempted writes during arbitrary voltage fluctuations outside of the recommended operating range (3.0-3.6V). However, the power-on-reset circuit does prevent writes to the PROM during a critical period at power-up.

Accidental writes from noise on the JTAG pins at power-up/down are very unlikely because an exact and lengthy serial sequence must be achieved. Internal pull-ups on the JTAG pins also prevent undesired activity on these signals.

If you are concerned that the PROM data output goes to the D[0-7] pins when power is outside the recommended operating range, you can use an external power-monitor device to pull either OE/RESET or CE to Low when power falls below 3.0V. When the PROM is used to configure a Virtex family FPGA, the power-monitor should hold either the FPGA PROGRAM or INIT pin Low during power-up until power reaches the recommended operating range. The decision to use either the PROGRAM or INIT pin depends on your desired result during a power sag. If power drops below the power-monitor's threshold, it will RESET the FPGA if the power-monitor controls the PROGRAM pin.

AR# 14444
Date 12/15/2012
Status Active
Type General Article