UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 14455

4.1i CPLD CoolRunner XPLA3 Hprep6 - Designs utilizing input registers do not function properly on the board

Description

Keywords: 4.1i, 4.2i, CPLD, XPLA3, input register

Urgency: Hot

General Description:
In designs utilizing input registers, the design may not function properly on the board, even though it has passed timing simulation.

Solution

To work around this issue, disable Fast Input Register usage. This can be done in the WebPACK/Foundation ISE "Implement Design" properties or via the command line through use of the "-inreg off" switch.

This problem is fixed in the latest 4.2i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 4.2i Service Pack 3.
AR# 14455
Date Created 04/11/2002
Last Updated 08/06/2003
Status Archive
Type General Article