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AR# 14518

5.1i CORE Generator - Asynchronous FIFO outputs RD_COUNT and WR_COUNT do not increment/decrement properly in simulation

Description

General Description:

When I run the simulation (behavioral and timing) process, the RD_COUNT and WR_COUNT outputs do not increment or decrement properly. This behavior occurs in simulation (behavioral and timing) as well as in the device.

Solution

This failure is more apparent when the RD_CLK and WR_CLK are running asynchronously and when read and write operations are being performed simultaneously.

This issue occurs because of the asynchronous nature of the core. This is not a bug in the Asynchronous FIFO core, but is rather a limitation of asynchronous cores.

The WR_COUNT and RD_COUNT values should NOT be used to obtain the accurate data count of the Asynchronous FIFO, as the value may be off by a few counts at any given time. The WR_COUNT and RD_COUNT should be used as a gauge to determine the FIFO status. Although the outputs of the RD_COUNT and WR_COUNT values appear to be incorrect, the basic functionality of the Asynchronous FIFO is not affected, and it will continue to read and write properly.

AR# 14518
Date Created 08/29/2007
Last Updated 12/15/2012
Status Active
Type General Article