How do I connect the VREF and VTST pins on the PCIV cable to my board?
The Parallel Cable IV uses the VREF pin as a reference voltage for the target device -- it determines the voltage level at which the PCIV cable will drive its outputs.
To determine the correct voltage level for VREF, review the DC switching thresholds for all devices in the chain and set VREF at a voltage level that will satisfy the VIHmin requirement of all inputs without exceeding the maximum input voltage of any device.
Most JTAG chains are driven at either 5V, 3.3V, or 2.5V.
Note: Most Xilinx FPGA devices contain VREF pins. These VREF pins have nothing to do with the PCIV cable VREF pins, and the two should not be connected.
The VTST is provided for future testing functionality, and it should not be connected to anything on the target board.
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