When a design is synthesized with XST, the clock input to a DCM does not appear in the Constraints Editor "Global" tab. OFFSET constraints cannot be created in the tool, as they require a clock input pad to be specified from the Global tab. The PERIOD constraints are not related by default, which causes any cross-clock domain paths to be ignored during timing analysis.
This bug relates only to Constraints Editor -- the DCM will work correctly throughout the rest of the implementation flow.
To work around this problem, manually enter the PERIOD and OFFSET constraints into the .ucf file. Timing analysis by TRCE, Timing Analyzer, and PAR will be performed correctly.
This issue will be fixed in a future version of the software.
The use of a DLL primitive will allow the pad clock net to appear in the Global tab.
The use of FPGA Express as a synthesis tool will allow the pad clock net to appear in the Global tab.