AR# 14548


4.2i CORE Generator - VCS simulation error occurs due to an inefficient register construct in the BLKMEMDP_V4_0.v file


Keywords: COREGen, VCS, simulation, block, memory

Urgency: Standard

General Description:
When I simulate Asynchronous FIFO or Dual-Port Block Memory using a VCS simulator, an error reports "index out of bound".

This error occurs because the file "BLKMEMDP_V4_0.v" contains the following vector definition:
reg [c_depth_a*c_width_a-1 : 0] mem;

c_width_a = 135 (c_data_width)
c_depth_a = 8191 (c_fifo_depth)

When you multiply these two numbers together, the resulting vector is large enough to hold the FIFO data as a single vector (1,105,785 bits). This can be done, but it appears that it should be represented as an array (memory element). This will improve simulation performance and make debugging quite a bit easier, as designers tend to think of a real array rather than a long linear vector that is indexed. Although the underlying implementation may be similar, the performance will differ.
AR# 14548
Date 10/08/2003
Status Archive
Type General Article
People Also Viewed