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AR# 14578

9.1i Timing Analyzer/PAR - The timing report and the PAR clock table report different clock skew values


Why does the timing report and the PAR clock table report different clock skew values?


This discrepancy occurs because of the differing ways in which the clock skew is calculated. The detailed timing path report analyzes the entire clock path when calculating clock skew. This includes pad delay, global buffer delay, and multiple net delays.

However, the clock table in PAR calculates clock skew based only on the clock net. PAR determines the worse-case skew on the clock net and reports this in the clock table.

This behavior is identical to the MAXSKEW constraint. If you specify this constraint, the reported figure is the same skew value as the clock table, except when the clock net is connected to output pads or slice inputs. PAR only reports the clock skew on paths to CLK pins, while the MAXSKEW constraint also includes paths going to output pads and slice inputs.

AR# 14578
Date 01/18/2010
Status Archive
Type General Article
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