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AR# 14581

Virtex-II/-II Pro, BUFGMUX - When S is set to "1" on power-up, the simulation output is unknown until the first falling edge on I1

Description

When the user sets the BUFGMUX input to "S=1" on power-up, the output is unknown until the first falling edge on I1; at that point, the output is set to I1. Is this the correct BUFGMUX behavior?

Please see the simulation figure below:

Simulating BUFGMUX with S= 1
Simulating BUFGMUX with S= 1

Solution

The simulation behavior is correct -- BUFGMUX always powers up with "I0" selected. Consequently, if "S=1" at "time=0", I0 is immediately de-selected as output and I1 is selected at its next falling edge.

The result is illustrated in the above simulation.

The BUFGMUX output O will be logic level "0" (GND) when S is changing from I0 to I1, and vice-versa.

For more information on BUFGMUX behavior, see the Virtex-II/-II Pro User Guides:

Virtex-II Pro

1. Refer to the "Virtex-II Pro and Virtex-II Pro X FPGA User Guide" at:

http://www.xilinx.com/support/documentation/index.htm
2. Select Virtex-II Pro under "FPGA Device Families."

3. Select Virtex-II Pro and Virtex-II Pro X FPGA User Guide.

4. Select Design Considerations -> Global Clock Networks.

Virtex-II

1. Refer to the "Virtex-II Platform FPGA User Guide" at:

http://www.xilinx.com/support/documentation/index.htm
2. Select Virtex-II under "FPGA Device Families."

3. Select Virtex-II Platform FPGA User Guide.

4. Select Design Considerations -> Using Global Clock Networks.

AR# 14581
Date Created 08/29/2007
Last Updated 12/15/2012
Status Active
Type General Article