UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 14603

SIMULATION, DCM - CLKDV output aligns with the falling edge of CLK0 instead of the rising edge of CLK0

Description

The clock divide output (CLKDV) aligns with the falling edge of CLK0 instead of the rising edge of CLK0 (this has only been observed when the DCM reset pulse is asserted for less than one clock cycle).

Solution

To avoid this problem, always assert the DCM reset for more than one clock cycle.

AR# 14603
Date Created 08/29/2007
Last Updated 05/14/2014
Status Archive
Type General Article