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AR# 1462

EXEMPLAR - How do I prevent LeonardoSpectrum from inserting a BUFG?

Description

Keywords: BUFG, insert, Virtex, prevent, none

Urgency: Standard

General Description:
How do I prevent LeonardoSpectrum from inserting a BUFG?

Solution

1

Pass the "buffer_sig" attribute as a synthesis directive. For more information regarding passing attributes, please see the LeonardoSpectrum Reference Manual.

VHDL:

library ieee;
use ieee.std_logic_1164.all;

entity ff is
port (d, clk : in std_logic;
q : out std_logic);

end entity;

architecture ff_arch of ff is

attribute buffer_sig : string;
attribute buffer_sig of clk : signal is "none";

begin

process (clk) is begin
if clk'event and clk = '1' then
q <= d;
end if;
end process;

end architecture;

2

Pass the "buffer_sig" attribute as a synthesis directive. For more information regarding passing attributes, please see the LeonardoSpectrum Reference Manual.

Verilog:

module ff (d, clk, q);

input d, clk;
output q;

reg q;

always @(posedge clk) q <= d;
//exemplar attribute clk buffer_sig none

endmodule
AR# 1462
Date 04/23/2007
Status Archive
Type General Article