When I synthesize a Verilog design with XST, the following error occurs:
"ERROR:Xst:79 - Model 'and4b1' has different characteristics in destination library."
In the error above, "and4b1" is the name of my model.
When you instantiate components from a Xilinx or user library, be sure to match component names and pins exactly. Verilog is case-sensitive, and if the case of the module name in your instantiation does not match the case of the module declaration, this error will occur.
In this case, "and4b1" is not the same as "AND4B1".