When I translate a design that instantiates a CORE Generator FIFO and contains a timing constraint that refers to the element group BRAMS_PORTA, the following warnings and errors occur during the translate process:
"WARNING:XdmHelpers:612 - Predefined group "BRAMS_PORTA" is empty because the design does not contain any elements of that type. This group is used in the following groups and/or specifications:
TS_01=FROM FFS TO BRAMS_PORTA 10000.000000 pS"
"WARNING:XdmHelpers:644 - No appropriate elements were found for the TNM group "BRAMS_PORTA". This group has been removed from the design."
"ERROR:XdmHelpers:648 - The specification "TS_01" is invalid because its TO group (BRAMS_PORTA) was removed. Checking expanded design ..."
"WARNING:NgdBuild:479 - The input pad net 'xlxn_29' is driving one or more clock loads that should only use a dedicated clock buffer. This could result in large clock skews on this net. Check whether the correct type of BUF is being used to drive the clock buffer."
One possible way to work around constraining the BRAM would be to use the "RAMS" keyword instead of BRAMS_PORTA/ BRAMS_PORTB.
Unfortunately, this action will not allow you to constrain Port A and Port B independently. However, the implementation tools do have the ability to apply different constraints to each half of the BRAM based upon your constraints on each half.