I wish to ignore a large number of paths in my design. In the design, all the paths end up at the same destination register; however, if I specify a TIG FROM the timing group "FFS" (all flip-flops) TO the destination flip-flop (after creating a timing group for it), the paths are still analyzed. My "source" and "destination" FFs are all clocked using the same clock, but these paths are not picked up by my FROM:TO TIG.
If a NET TIG is specified on the output net of the "source" flip-flops, in these paths will not be analyzed. (This will take some time, as you must find each individual net name.)