We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 14708

4.2i Foundation Schematic Editor - automatically makes use of I/O pins to connect macros in schematics


Keywords: 4.2, Foundation ADLEC, macro, Schematic EDITOR, I/O, VHDL.

I used the Schematics Editor, and implement the schematic design with macros that we have created from some VHDL code and other schematic.
When I implemented my new design, the Foundation software automatically makes use of I/O pins to connect ours macros.
My design then use more IOBs that it should normally use.

How can I avoid this situation?


The Implementation tool will use IOBs to connect the macros if your macros contain IBUF and OBUF buffers.

When you create your VHDL module and synthesize your code, the synthesis tool automatically add input and output buffers on the port pin into the netlist.
Therefore, when you create a macro from that netlist, the IBUFs and OBUFs being defined in the netlist, will also be added to the schematic macro.

When Interconnecting the different modules in the schematic, all the modules's interconnection will be made correctly and all the module's input and output will be connected to the IOBs too.

To avoid this problem:
Do not allow the synthesis tool to infer I/O pads into your modules when synthesizing the VHDL code.
Do not insert IBUF, OPAD, IPAD, OPAD in your schematic modules.

For VHDL code
Before running the synthesis, uncheck the option: "Insert I/O pads" in the synthesis settings.

1. Clear the implementation data.
2. In Project manager, double click on the Synthesis button.
3. In the new opened window (Synthesis/Implementation settings), click on SET next to synthesis settings.
4. Run the synthesis.
5. generate the macro from the new created netlist.
AR# 14708
Date 04/27/2006
Status Archive
Type General Article