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AR# 14753

4.2i iMPACT - When I use the verify command line option in batch "File Generation" mode, incorrect TDO values are written to the SVF file

Description

General Description:  

In the 4.2i iMPACT Programmer, when I use the verify command line option in File Generation Mode, incorrect TDO values are written to the SVF file. 

 

For example

 

impact -batch 

setmode -bsfile 

setcable -p svf -file test.svf 

addevice -p 1 -file virtex.bit 

verify -p 1 

 

Within the SVF/STAPL file, the TDO values in the Verify section will all be "0"s.

Solution

When the SVF/STAPL File Generation Mode is used, the verify option should be disabled for all FPGA devices. 

 

This problem is fixed in the latest 4.2i Service Pack, available at:  

http://support.xilinx.com/support/techsup/sw_updates  

The first service pack containing the fix is 4.2i Service Pack 3.  

 

NOTE: At this time, the verify operation for FPGA devices is only supported in software when a programming cable is used directly with the iMPACT programmer.

AR# 14753
Date Created 08/29/2007
Last Updated 05/14/2014
Status Archive
Type General Article