Previously, the clock-to-out time of the variable phase shift status signal "PSDONE" was relative to the CLKIN input of the DCM. It is now relative to PSCLK.
To include this change in the report, regenerate the timing report using TRCE or Timing Analyzer. Note that PSDONE will take multiple clock cycles to become asserted after PSCLK.
This problem is fixed in the latest 4.2i Service Pack, available at:
The first service pack containing the fix is 4.2i Service Pack 3.