AR# 14823

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6.1i ISE- "ERROR: Xst - xxx.vf Line xxx. parse error, expecting `error' or `','' or `')'' is reported when I synthesize an ECS schematic in XST-Verilog

Description

Keywords: bus, delimiter, synthesize, synthesis, I/O, markers, illegal, VHDL, bus

Urgency: Standard

General Description:
When I synthesize an ECS schematic in XST-Verilog, the following errors are reported:

"ERROR:Xst - xxx.vf Line xxx. parse error, expecting `error' or `','' or `')''
"ERROR:Xst - xxx.vf Line xxx. parse error, expecting `';''

Solution

When naming I/O markers, especially when doing so from a bus, you cannot use the following characters: (), {}, or []. If these brackets are used, illegal VHDL code will be created within the ".vhf" file in the port declaration.

To work around this restriction, add a buffer between the bus tap net and the I/O marker; give the I/O marker a name that does not contain (), {}, or [].

7.1i will allow bus names for I/O markers.
AR# 14823
Date 01/08/2006
Status Archive
Type General Article
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