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AR# 14850

5.1i CORE Generator - When I use the IP Capture tool, it reports "ERROR: Cannot open file <./XilinxCoreLib/vhdl_analyze_order> for writing. No analyze order list will be generated"

Description

Keywords: IP Capture Tool, COREGen, analyze_order, CoreLib, get_models

Urgency: Standard

General Description:
When I attempt to capture IP with the IP Capture tool, the simulation files are not set up properly, and the following error message is reported when I run "get_models -vhdl -dest":

"Destination directory chosen for simulation models to be copied to is:
<.>.
The Xilinx models will be in the subdirectory named: <XilinxCoreLib>.

The following vendors were located:
<foo> : VHDL files copied: 281
VHDL files copied: 281

A total of 281 VHDL files have been copied.

For information on the proper order in which the extracted VHDL models must be analyzed, see:
<./XilinxCoreLib/vhdl_analyze_order>

ERROR: Cannot open file <./XilinxCoreLib/vhdl_analyze_order>for writing. No analyze order list will be generated."

Solution

This error occurs because the library name "XilinxCoreLib" is hard-coded into the analyze order file generation code. As a result, the analyze order file is not written out, as it should be using "<VendorName>CoreLib" instead.

If you change the name of the $XILINX/coregen/ip/xilinx directory to "$XILINX/coregen/ip/foo", a "FooCoreLib" library directory is created in $XILINX/vhdl/src. However, the code that generates the analyze order file contains the hard-coded XilinxCoreLib name, and the above error is reported.
AR# 14850
Date Created 08/29/2007
Last Updated 03/04/2008
Status Archive
Type General Article