A SPI 4.2 (PL4) core is included in my design. When I run BitGen, the following error is reported:
"ERROR:DesignRules:524 - Blockcheck: Incomplete DCM configuration. The DCM comp pl4_snk_top0/pl4_snk_clk0/rdclk_dcm0 is set for variable phase-shifting with CLKOUT_PHASE_SHIFT set to VARIABLE. Therefore the phase shift pins (PSINCDEC, PSEN, and PSCLK) must have active signals."
This problem is fixed in v5.2 of the SPI 4.2 core.
Xilinx recommends that if you are using v4.x of the SPI 4.2 core, you should upgrade to v5.2 or later.
The Design Rule Check (DRC) program, which is executed at the time of the bit file generation, issues this message. This error is an indication that the bit file cannot be generated.
If the v4.x core cannot be upgraded, you can run BitGen with the DRC disabled (it is enabled by default). If the above error is the only error reported, you can safely turn the DRC "Off" in the BitGen options and re-run BitGen to generate the bit file. To turn off the DRC program in BitGen, run BitGen from the command line, using the "-d" option.