General Description:
How do I force the fitter to use the global clock, global output enable, or global set/reset resources?
(NOTE: For the global buffers to be used, the only logic allowed between the buffer and the destination [CLK, OE, reset] pins is an inverter.)
Global Clock:
If the clock signal is generated external to the device, simply connect the input pad to a BUFG, then connect the output of the BUFG to the register's clock inputs.
This signal will then be automatically routed to a Global Clock pin. If you want it to map to a specific GCLK pin, use pin-locking to constrain the pin.
For information on pin-locking, please see (Xilinx Answer 2719).
If the signal is internally generated, please see (Xilinx Answer 5572).
Global Output Enable:
If the signal comes from an input pin, simply connect a BUFGTS between the input and the OE for the 3-state lines.
If you wish to use a specific BUFGTS pin, pin-assign that input signal to the desired pin.
For information on pin-locking, please see (Xilinx Answer 2719).
If the signal is internally generated, please see (Xilinx Answer 5572).
Global Set Reset:
If the signal comes from an input pin, simply connect a BUFGSR between the input and the set or reset of the registers.
If the signal is internally generated, please see (Xilinx Answer 5572).
AR# 1489 | |
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Date | 12/15/2012 |
Status | Active |
Type | General Article |