TAEngine does not report timespec violations with respect to negative edge-triggered registers.
For example, a period constraint of 20 ns with a 50/50 duty cycle has a critical path from regA (positive edge-triggered) to regB (negative edge-triggered) at 11 ns. This should be a violation of the timing constraint; however, this is not reported as a failing path.
This problem is fixed in the latest 5.1i Service Pack, available at:
The first service pack containing the fix is 5.1i Service Pack 1.