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AR# 15012

5.1i CPLD TAEngine - A PERIOD constraint fails to analyze negative edge-triggered registers

Description

General Description: 

TAEngine does not report timespec violations with respect to negative edge-triggered registers.  

 

For example, a period constraint of 20 ns with a 50/50 duty cycle has a critical path from regA (positive edge-triggered) to regB (negative edge-triggered) at 11 ns. This should be a violation of the timing constraint; however, this is not reported as a failing path.

Solution

This problem is fixed in the latest 5.1i Service Pack, available at:  

http://support.xilinx.com/support/techsup/sw_updates  

The first service pack containing the fix is 5.1i Service Pack 1.

AR# 15012
Date Created 09/03/2007
Last Updated 05/08/2014
Status Archive
Type General Article