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AR# 15149

XST - Can I pass an INIT constraint to a flip-flop through an HDL signal initialization construct?

Description

Are VHDL/Verilog initialization constructs such as the following recognized by XST? 

signal a : std_logic := '1'; 


reg a = 1'b1;

Solution

Yes. For more information, refer to the XST User Guide at: 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/ise_n_xst_user_guide.htm

AR# 15149
Date Created 07/15/2002
Last Updated 10/05/2016
Status Active
Type General Article