AR# 15149


XST - Can I pass an INIT constraint to a flip-flop through an HDL signal initialization construct?


Are VHDL/Verilog initialization constructs such as the following recognized by XST? 

signal a : std_logic := '1'; 

reg a = 1'b1;


Yes. For more information, refer to the XST User Guide at:

AR# 15149
Date 10/05/2016
Status Active
Type General Article
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