We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 15178

Innoveda - VSM reports "Error: viewbase: Error 338: Undefined variable(s) encountered..." for parameterized attributes


Keywords: Innoveda, EPD, eProduct, parameterized attribute, FLOATVAL, Virtex-II, VSM, netlist, wir, library

Urgency: Standard

General Description:
When I generate a simulation netlist using Innoveda's ViewSim VSM netlister, VSM issues an error similar to the following:

"Error: viewbase: Error 338: Undefined variable(s) encountered (FLOATVAL=@INIT).
Occurred on net instance $1|2\$1|6\GSR_INIT0"


This problem occurs in hierarchical schematic designs in which a Xilinx primitive with a parameterized attribute is placed in a lower level schematic macro.

For example:

- An FDS symbol from the Virtex-II library is placed in a schematic sheet named "MY_COMP".
- The FDS contains a parameterized attribute "INIT".
- A hierarchical symbol named MY_COMP (based on the MY_COMP schematic sheet) is instantiated into the top-level design.

An error will be reported for the INIT during the generation of the top-level design's VSM netlist.

However, if you generate the VSM on the "my_comp" schematic level, no error will be reported.

The VSM problem is independent of the Xilinx implementation flow and applies to Virtex-II and newer devices only. This is a simulation-only issue -- the attributes in question have been verified to work correctly in the implemented design.

To work around this simulation problem, you may simulate individual modules using ViewSim and VSM. However, to simulate the entire design, you should use another third-party simulation tool.

- For functional simulation, export an EDIF file, run NGDBuild, and use NGD2VER or NGD2VHDL to generate a simulation HDL file.
- For timing simulation, complete implementation, and use NGD2VER or NGD2VHDL to generate a simulation file.
AR# 15178
Date 10/01/2008
Status Archive
Type General Article