AR# 15179: SYNPLIFY 7.x - Synplify reports that I have used "x out of 8" BUFGs (clocks) in a Virtex-II part (Virtex-II devices contain 16 BUFGs)
SYNPLIFY 7.x - Synplify reports that I have used "x out of 8" BUFGs (clocks) in a Virtex-II part (Virtex-II devices contain 16 BUFGs)
Keywords: Synplify, Virtex, II, BUFG, 8, 16
General Description: In the mapping section of the Synplify log file, the report states that there are a maximum of 8 global buffers (BUFG) for the Virtex-II. Is this correct?
This is a reporting error -- 16 BUFGs are available in a Virtex-II device; however, Synplify will only use up to 8 BUFGs.
To overcome the 8 BUFG limit, use the "xc_global_buffers" constraint in an .sdc file in your Synplify project. The following definition is from Synplify's online help information:
Attribute; Xilinx. Controls the number of global buffers used in a design. The Synplify Pro synthesis tool automatically adds global buffers for clock nets with high fanout. Use this attribute to specify a maximum number of buffers and restrict the amount of global buffer resources added. Also, if there is a black box in the design that has global buffers, you can use xc_global_buffers to prevent the synthesis tool from inferring clock buffers and exceeding the number of global resources. You can only specify this attribute through a constraint file (cannot be specified in HDL source code).