In System Generator for DSP v2.2, timing groups are created through the use of clock enable nets. In my Single-Port Distributed RAM block, the core is not using the clock enable net. This means that all distributed RAMs must run at the system rate -- this problem prevents me from meeting my timing requirement.
A patch to fix this bug will be available in mid-November, 2002.
If you require this patch before then, please contact Xilinx Customer Service by opening a WebCase at: