UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 15194

5.1i, Architecture Wizard - When I configure a DCM with an external feedback, the DCM Wizard connects CLK0 or CLK2X to a BUFG. Is this correct?

Description

General Description:

When I configure a DCM with an external feedback, the DCM Wizard connects CLK0 or CLK2X to a global buffer (BUFG). Why does DCM Wizard set this as the default connection? I expected to have CLK0/CLK2X connected to an output buffer so it could be brought from the FPGA.

Solution

This default connection is intentional and is designed to give you flexibility in implementing an external feedback. With an external feedback selection, the DCM Wizard will automatically connect a CLKFB input to an IBUFG.

You may choose to output CLK0/CLK2X via a global buffer (BUFG) or an output buffer (OBUF) for optimum external feedback.

The following examples illustrate each choice:

1. Use of a global buffer (default) with a DDR using local inversion

- The DCM Wizard instantiates the global buffer (BUFG).

- In your design, connect the BUFG output to a DDR output flip-flop as in the following figure:

External feedback with a BUFG and DDR using local inversion
External feedback with a BUFG and DDR using local inversion

(NOTE: Do not connect the BUFG output to an OBUF, as the BUFG output must use a local interconnect to reach the OBUF. If you wish to use an OBUF for your external feedback, use Scenario 2 below.)

2. Use of an OBUF

- Select "Local Routing" in the "Clock Buffer" column of the "Clock Buffers" window.

- In your design, connect that output to an output pin via an OBUF as illustrated in following figure:

External feedback with an OBUF
External feedback with an OBUF

3. Use of a global buffer with a DDR output flip-flop

(This is similar to Scenario 1.)

- Depending on whether you are using a 1X or 2X feedback, select CLK0/CLK2X with CLK180/CLK2X180, respectively.

- Select BUFG in the "Clock Buffer" column for this output.

- In your design, connect the CLK0/CLK2X to C0, CLK180/CLK2X180 to C1 of an OFDDR as illustrated in the following figure:

External feedback with an OFDDR
External feedback with an OFDDR

(NOTE: This scenario is best for high-speed applications that require 50/50 duty cycles. Please see (Xilinx Answer 12406) for more information.)

AR# 15194
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article