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AR# 15233

6.1i Virtex-II PAR - The placer fails to handle SelectIO requirements when more than eight clocks are present

Description

Keywords: ERROR:Place:181, SelectIO, SelectI/O

Urgency: Standard

General Description:
When a Virtex-II design contains more than eight clocks, or when the design contains two clock buffers locked to the same primary/secondary pair and the I/O logic is not constrained, the placer to automatically constrains I/O to quadrants so that the primary/secondary pairs do not drive loads in the same region. When this occurs, the following warning message is reported:

"WARNING:Place:83 - This design either uses more than 8 clock buffers or has clock buffers locked into primary and secondary sites. Since only one clock buffer output signal from a primary/secondary pair may enter any quadrant ..."

In this situation, the placer will not always perform automatic constraining to meet SelectIO banking rules. This will cause the placer to report the following error:

"ERROR:Place:181 - Possibly, due to SelectIO banking constraints, the placer was unable to find a feasible solution for the IOBs in your design.

Each Group of a specific Standard is listed.
Standard LVCMOS33 (Vref=NR Vcco=3.30 Terminate=none) 4 IOs, 1 locked.
(1-Inputs, 3-Outputs, 0-Bidirectional)
Standard LVCMOS25 (Vref=NR Vcco=2.50 Terminate=none) 4 IOs, 1 locked.
(1-Inputs, 3-Outputs, 0-Bidirectional)
Standard LVCMOS18 (Vref=NR Vcco=1.80 Terminate=none) 4 IOs, 1 locked.
(1-Inputs, 3-Outputs, 0-Bidirectional)"

Solution

This problem will be fixed in the next major software release after 6.1i.

For the time being, you may work around this problem by constraining SelectIO components to banks so that all banking rules are met.
AR# 15233
Date Created 09/03/2007
Last Updated 10/20/2008
Status Archive
Type General Article