AR# 15282


8.1i MAP - Why does a signal get implemented as LVTTL when I set the IOSTANDARD constraint for LVDCI_33?


Keywords: LVDCI, LVTTL, constraint, implement

When I set the IOSTANDARD to LVDCI_33, the I/O shows up in the pad report and in FPGA Editor as LVTTL.


If an IOSTANDARD is not set correctly, MAP will print the following warning message and then choose a default value.

"One or more IO components has an illegal property value..."

Check the MAP Report (.mrp) for warnings and verify that the constraint is set correctly. The syntax should be as follows:

AR# 15282
Date 05/05/2009
Status Archive
Type General Article
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