This Answer Record answers frequently asked questions regarding Amplify physical synthesis.
Q: What is "physical synthesis"?
A: Physical synthesis is the process of performing simultaneous placement and logic optimization.
Unlike logic synthesis, it generates placement along with an improved netlist that is specifically optimized for a user's floorplan.
Q: Why is physical synthesis needed?
A: New applications demanding high performance are being implemented using large FPGA devices such as Virtex-II and Virtex-II Pro.
Meeting these tough design goals in a reasonable time frame requires addressing complex issues early in the design cycle.
Since interconnect delay is the most dominant issue that controls both performance and time to market, incorporating its effects up-front is critical.
Physical synthesis allows simultaneous consideration of the interconnect and logic-related issues very early in the design cycle.
Consequently, it is a tremendous help in achieving the design goals and in turn the financial goals.
Q: How many customers have benefited from Amplify physical synthesis?
A: Just within the two years since its introduction, more than 130 companies have used Amplify successfully to achieve their design goals.
Q: When is Amplify useful?
A: You can use Amplify to improve timing performance to reach a difficult design goal quickly.
For applications using large volumes of FPGA parts, Amplify can be used to improve performance such that the same design can be implemented using a slower and cheaper speed grade.
For large projects, Amplify's team design capabilities can be used independently to manage the functional and timing domains of the design.
Q: How is Amplify used?
A: You can use Amplify in two basic ways: interactive and automated.
While the interactive flow generally gives the best performance improvement, the automated flow can provide a very fast boost without adding any additional constraints for synthesis.
The interactive flow requires the user to create physical regions on the device and assign critical path logic to it.
The automated flow does not require this.
Q: What is TOPS?
A: TOPS stands for Total Optimization Physical Synthesis.
This is a name Synplicity has given to its second-generation physical synthesis technology.
TOPS adds two elements to the existing Amplify product:
1. It improves the existing interactive flow - Interactive TOPS (ITOPS)
2. It enables the fully automated flow - Automated TOPS (ATOPS)
Q: What is ITOPS?
A: Interactive Total Optimization Physical Synthesis (ITOPS) can be used in an interactive mode to create regions on the device from the Amplify Physical Constraint editor as in previous versions of the Amplify flow.
Amplify ITOPS software constrains logic to specific placement locations, instead of letting the Xilinx PAR assign placement locations for all logic in a region.
The ITOPS option is enabled by default.
Typically, ITOPS provides an additional 10% improvement, which is on top of an average 25% performance improvement over logic synthesis through Amplify's standard interactive capabilities without ITOPS.
ITOPS is exclusive to Xilinx devices, including Virtex, Virtex-E, Virtex-II and Virtex-II Pro.
Q: How is the interactive physical synthesis flow (ITOPS) in Amplify used?
A: The interactive physical synthesis flow is used for fast timing closure or when a more significant (up to 35%) performance improvement is needed without RTL code changes.
Improvements of greater than 35% usually require HDL code changes.
Amplify's interactive features allow a user to create an RTL floorplan of the design which is used to guide physical synthesis.
This may be performed up front (before PAR) or after an initial PAR run has been completed.
A new automatic extraction of physical hierarchy (an "Island-based" timing report) is created to let the user know what logic needs to be physically constrained (floor planned).
Built-in design rule checks notify the user right away if the regions they created need to be resized and if resources like block RAM have been exceeded.
Once the floor plan is complete, Amplify uses this information to perform physical synthesis, including full, detailed placement of logic in the regions defined by the floor plan.
Detailed placement is performed for Virtex, Virtex-E, Virtex-II and Virtex-II Pro devices.
Regional placement is performed for Spartan-II and Spartan-3 devices.
The automated flow mentioned above can be used after PAR in the interactive flow as well.
Q: What is ATOPS?
A: Automated Total Optimization Physical Synthesis (ATOPS) allows users to quickly incorporate post-PAR timing and placement information for incremental logic and detailed placement optimizations.
There is no need to manually create an RTL floorplan.
This flow is designed to achieve moderate performance improvement quickly.
Typically, ATOPS provides an average improvement of 8% over logic synthesis.
Note that the Xilinx PAR_BELDLYPRT environment variable must be set when running ISE Alliance to get appropriate post-PAR timing information.
ATOPS is exclusive to Xilinx devices, including Virtex, Virtex-E, Virtex-II, and Virtex-II Pro.
Q: How much does Amplify improve performance?
A: Achieving good performance improvement depends upon the individual design.
Constraints, the device used, and utilization also impact performance.
For Datapath designs, users can create regions to model the data flow and assign proper logic blocks to those regions.
For random logic, users can search for critical paths and place those critical paths in regions for controlling delay.
For all designs, a combination of the above two, along with creating regions next to critical I/Os, block RAMs, and RocketIO Multi-Gigabit Transceiver blocks can improve results significantly.
An average of a 25% improvement versus logic synthesis alone has been observed on Virtex designs when the interactive methodology is used (the range is from 0% to over 50%, depending upon the quality of the physical constraints applied).
The automated flow has demonstrated an average of over 8% for Virtex-II designs, with a range of 0% to over 25%.
Q: How easy is Amplify to use?
A: As a tool, Amplify is easy to use.
It builds onto Synplify Pro and maintains the same look and feel. It provides a very intuitive GUI for creating physical constraints.
The primary requirement for achieving desired performance quickly with Amplify's interactive flow is familiarity with the design itself.
Amplify's automated flow is completely push-button once normal timing requirements have been specified.
Q: How is the automated physical synthesis flow (ATOPS) in Amplify used?
A: The automated flow in Amplify is used when a quick, moderate (up to 10%) performance increase is needed.
This can be run immediately after an initial synthesis and P&R run (no physical constraints / floor plan) or after a floor plan has been created using the interactive features of Amplify and placed and routed.
Placement and timing delay from the initial P&R is used as input to Amplify's automated flow and then it performs re-synthesis and placement of critical paths.
The output is a fully placed design ready for final routing in ISE.
The automated flow may be repeated 2 to 3 times and in some cases may result in further improvement.
The automated flow is available for Virtex-II and Virtex-II Pro devices.
Results are very design dependent, but because it is fully automated, it is easy to try on your design.
Q: What are the salient capabilities of Amplify?
A: Amplify provides an easy-to-use GUI for creating physical constraints, including logic assignment, pin assignment, and manual and auto replication--using these elements to deliver superior performance.
Amplify also allows users to perform netlist restructuring without modifying the HDL code.
Q: What netlist restructuring capabilities does Amplify provide?
A: Amplify provides zippering to break large modules into smaller manageable modules.
Cones of logic are traced from input pins of the module and put into separate smaller modules.
These smaller modules can then be assigned to proper physical locations for better placement and timing.
It also provides bit-slicing to break large busses into smaller slices for better placement and optimization.
Users can specify the number of slices to be created.
Both zippering and bit-slicing operations are specified through an easy-to-use GUI, and no RTL code changes are necessary.
Q: Isn't Amplify simply a floorplanning tool? What is the difference between Amplify and Xilinx Floorplanner?
A: Absolutely not.
Floorplanners take an already-synthesized netlist and allow a user to create manual placement for selected regions of their design.
This can certainly help performance, but Amplify goes well beyond this to perform either fully automated placement (in the automated flow) or guided placement (in the interactive flow), while at the same time performing logic optimizations which can result in fewer levels of logic on a critical path.
In other words, Amplify not only performs automatic detailed placement, but can at the same time improve the netlist for performance.
Xilinx Floorplanner cannot change the netlist; it can only assist the user in manually specifying placement.
Q: What Xilinx devices are supported by Amplify?
A: Amplify supports:
- Standard Interactive Mode: Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Spartan-II, Spartan-IIE and Spartan-3
- ITOPS: Virtex, Virtex-E, Virtex-II and Virtex-II Pro
- ATOPS: Virtex, Virtex-E, Virtex-II and Virtex-II Pro
Q: Does Amplify support the Xilinx modular flow?
A: Yes. Amplify allows the creation of hard PAR regions and I/O regions along with the normal block regions used for non-modular flow.
It creates a directory structure suitable for modular flow and generates multiple EDIF netlists and NCF constraints for independent modules.
Q: Does Amplify support the Xilinx incremental flow?
A: Yes. Amplify allows creation of multiple area groups, EDIF netlists, and NCF files through use of PAR regions.
These separate netlists and constraint files can then be used with ISE Alliance tools to follow the incremental flow methodology.
Q: What is required to run Amplify for Incremental Flow or Modular Flow?
A: The Amplify license must contain the "modular" feature.
Q: What is the gated clock conversion feature in Amplify? How is it activated?
A: Automatic gated clock conversion enables designers to use ASIC RTL code to target an FPGA device without any modifications.
Typically, ASIC designs use gated clocks for power control.
Without this feature, most ASIC designs synthesized in FPGAs have hold violations and require manual changes to the RTL.
This feature was previously implemented in Certify.
Many customers have identified this as a key technology that enables rapid conversion of ASIC designs into FPGAs.
This feature will be activated if the user holds a Certify license.
Q: What should I watch for when using Amplify?
A: Use care when specifying overlapping area constraints, because this is not recommended for the ISE Alliance flow.
Q: Where do I find documentation for Amplify that is not online?
A: Please visit the Synplicity web site at: http://www.synplicity.com/literature/index.html#amplify.
Q: Is Amplify integrated into ISE in the way as Synplify and Synplify Pro?
A: No. You cannot invoke Amplify from ISE, but you can invoke Project Navigator from Amplify in the same way that you can invoke Project Navigator from Synplify (Pro).