This Answer Record contains a list of Frequently Asked Questions for the Xilinx Synthesis Technology (XST).
Solution
This synthesis tool is fully integrated within the ISE software environment. The following questions and answers correspond to the 9.1i release of XST.
Q: What architectures does XST support?
A: XST supports the following families: FPGA: Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4, Virtex-5, Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E, Spartan-3A. CPLD: XC9500, XC9500XL, XC9500XV, CoolRunner, CoolRunner-II. XST does not (and never will) support XC4000 family FPGAs, including Spartan and Spartan-XL.
Q: What is the quality of results obtained by XST?
A: XST is considered by most to be as good as any of the other synthesis tools on the market. Sometimes it outperforms them, sometimes it does not, but that is true when comparing any two synthesis tools. XST has made steady progress from release to release, improving clock frequencies and decreasing area, as well as reducing run time and memory utilization. XST has been tuned for the Virtex architectures, inferring many of the specific primitives of the architecture. Users have extensive control over inference capabilities and optimization techniques via global options and local attributes.
Q: Is Xilinx competing with Synplicity and Mentor Graphics?
A: No. Xilinx is trying to provide an OEM type, low-cost replacement for FPGA Express, not replace Mentor Graphics or Synplicity seats. They will probably always be ahead of Xilinx in interactive user features that help complete the highest density, highest speed designs for a couple of reasons: One, Xilinx shares research into synthesis ideas with them, and two, Xilinx software development focuses on PAR and is split across many other applications. Because of their single-minded focus on synthesis and our partnership efforts to have them continue improving as quickly as they can, we expect them to stay ahead of Xilinx in synthesis. Finally, we want other companies working on synthesis for Xilinx, because Xilinx recognizes that not all the good ideas can come from our internal development groups.
Q: How extensive is XST language coverage?
A: With each release, XST is closing in on the defacto coverage set by other synthesis tools. It is estimated that the current language support covers at least 95% of the constructs supported by other synthesis tools. Many of the unsupported constructs are infrequently used or have simple work-arounds. Also, many of these constructs are not handled consistently by the other synthesis tools; one tool might accept a construct in one way, another in a different way, and the third might flag a parsing error. In some situations, XST is actually more precise than other tools, requiring exact, complete descriptions when other tools allow incomplete or vague code. These are very common issues when moving code from one synthesis tool to another.
Q: Does XST support Verilog 2001 or SystemVerilog?
A: Initial support of Verilog 2001 was included in the 5.1i release. XST now supports all but one (configurations) of the synthesizable features of Verilog 2001, and all these newly supported constructs are documented in the XST User Guide. Xilinx will continue to expand Verilog 2001 support with each new major and minor release of the software.
SystemVerilog is not yet supported by XST.
Q: Does XST support mixed VHDL/Verilog projects?
A: Yes, XST initiated support of mixed VHDL/Verilog projects in ISE Design Suite 6.1i. The flexibility of mixed language support will improve with each release, but most designs should have no problems being processed with the current tools. Use a black box flow to achieve mixed language synthesis with versions of XST prior to 6.1i.
Q: Why does XST produce NGC output files instead of EDIF?
A: In order to achieve better quality of results and improve the overall design flow, XST is moving towards tight integration of Synthesis and Implementation tools. Creation of NGC format files from synthesis is the first step required to build mapped designs.
Q: How can I read an NGC netlist?
A: ISE Design Suite includes a netlist translation tool called NGC2EDIF. This command-line utility has been developed for two reasons: 1) To view an EDIF representation of an XST design 2) To pass information to third party synthesis tools for black box utilization information. The output EDIF file, which has an NDF extension, should not be modified or implemented, because this flow is not tested.
Q: Does XST have a schematic viewer available?
A: Yes, an RTL viewer was introduced with the 5.1i release. This viewer opens NGR files (pre-optimization netlists from XST) in ECS in a read-only mode. XST 5.2i added support for RTL views of designs processed using Incremental Synthesis. Cross-probing from instances in the RTL schematic back to the HDL source is available. A technology viewer has been added in the 7.1i release of XST, allowing users to view the final NGC netlist created by XST. The quality and speed of RTL and Technology views were greatly improved in the 8.1i release.
Q: Does XST have a Physical Synthesis flow?
A: There are a few ways to look at Physical Synthesis, and there are a few things that XST is doing to support it. First, XST currently has a "Slice Packing" switch, which groups LUTs into slices during optimization. Not only does this provide more accurate timing information for optimization, but the slice packing information is passed to implementation for more consistency during mapping.
Looking forward, the XST team is developing two other flows that will improve estimation and overall results. First, XST will contain an internal placer and packer that will estimate place and route results and, therefore, provides more accurate wireload delays to be used during optimization. A second flow will read a routed NCD file to obtain actual placed and routed timing information for optimization.
Q: Is the synthesis flow for FPGAs and CPLDs timing driven?
A: The synthesis flow is timing driven for FPGAs, but not for CPLDs. XST accepts timing constraints to control optimization of FPGA flows. Accepted constraints include Period, Offset In Before, Offset Out After, Inpad To Outpad, Max Delay, and TIG. For CPLD flows, XST uses optimization techniques to improve timing via reducing the number of logic levels.
The XST log file includes a detailed timing report that shows all the clocks in the design with the type of clock buffer used and the number of loads for each. Wireload models are used to estimate maximum clock frequency as well as maximum input and output times. Detailed path coverage is listed for the critical paths for Period, Offset In Before, and Offset Out After constraints.
Q: Does XST support UCF-style timing constraints?
A: The first support of UCF-style timing constraints began with the 5.1i release. The flow is for users to define their timing constraints using the traditional methods (Constraints Editor, etc.), then copy these timing constraints into an XCF file. This new constraint file format supports synthesis and implementation constraints as well, but the syntax is different from UCF syntax. The XST User Guide contains syntax details.
The long-term goal is to support all constraints for Synthesis and Implementation through one constraint entry mechanism.
Q: What is the goal of the HDL Advisor?
A: The goal of the HDL Advisor is to provide expert analysis and appropriate feedback on designs to help identify potentially erroneous or inefficient coding styles and provide suggestions to achieve better results. XST issues specific messages when certain situations are detected. For example, if the user puts a KEEP constraint on a net and this constraint prevents XST from performing timing optimization, then it will inform the user that this is happening. Currently, all HDL Advisor messages are reported as Warnings or Info, and they are presented within the context of the current module. In future versions of XST, they will be tagged with an "HDL Advisor" heading, and may be grouped together in an HDL Advisor summary.
Q: Does XST support an Incremental Synthesis flow?
A: Yes, XST supports an Incremental Synthesis flow with the use of Partitions. When Partitions are set on a design module, its synthesized result is cut and pasted into the final netlist if the input sources that built it have not changed from one run to the next.
XST also supports incremental flows using the INCREMENTAL_SYNTHESIS attribute, either in the source itself, or within a constraints file. However, with the development of Partitions, support for this attribute and flow will be phased out.
Q: What does "Register Balancing" mean?
A: The goal of Register Balancing is meet design timing requirements by moving registers forwards or backwards through logic to increase clock frequency. This constraint can be controlled on a number of levels, including by clock tree. Control over register movement direction and at device pins is also offered.
Q: What kind of advantages are experienced using High Optimization Effort compared to Normal Effort?
A: Beginning with the 7.1i release, many advanced optimization techniques were added to the High Effort option in XST. When enabling this switch, expect a longer runtime, but in many cases that runtime is worth it, as the average clock speed improvement is 7%.
Q: What does the term "Equation Shaping" in regards to the CPLD flow mean?
A: The goal of this optimization technique is to optimize and reduce the Boolean equations to sizes accepted by device macrocells. This forces the CPLD fitter to respect the equation tailoring through "keep" and "collapse" constraints written into the NGC file.
Q: Is XST supported within XFLOW?
A: Yes. Use the -synth option to include XST synthesis with your XFLOW run. Option files for VHDL and Verilog are included with the software. Type "xflow" for help and option file names.
Q: Where can I find more information about XST?
A: Many resources are available to help users work around any difficulties they might experience: