When I run MAP on a Virtex-series device, the following warning occurs:
"Warning: Pack:266 - the function generator <> failed to merge with F5 multiplexer <>."
NOTE: Unless this problem is actually causing your design not to meet its timing requirements, this message is probably not relevant.
To obtain additional information on the problem indicated by this warning, open the project in FPGA Editor. Look for the ix1214 function generator (LUT) and the TCI2/ix1394 F5 multiplexor. The FXMUX feeds the "X" output of the slice, and one of the FXMUX inputs is driven by the F5 MUX. (A basic slice-routing diagram is available in the Virtex-E Data Sheet in "Figure 5: Detailed View of Virtex Slice" http://www.support.xilinx.com/partinfo/databook.htm#virtex.)
The warning is caused when the tool tries to optimize the design, but fails to push the F5 and LUT logic into the same slice. This might be due to design constraints. However, this should not present a problem if timing is still being met.
The following suggestions might help to debug the source of the warning message:
- Try to LOC both the LUT and the F5 mux in the same slice. The resulting error should report a specific reason.
- As the tools cannot merge these elements into the same slice, you can ensure that the synthesis tools did not place any locational constraints on these elements. Search the netlist for "set" (meaning, HSET, HUSET, USET) and "loc" constraints to be sure that no incorrect location constraints exist.