UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 15403

Virtex-II/Pro JTAG - Instruction_Capture bits are incorrect when TAP is moved to Pause-IR state

Description

Most Xilinx devices implement the JTAG Instruction Capture register. This register is accessed by moving to the Capture-IR state and then to the Shift-IR state and clocking TCK. The Instruction Capture register typically contains information about the status of the device (i.e., whether the DONE pin is released, etc.) The meaning of each of the Instruction Capture bits is described in the device BSDL file.

There are two potential problems with the Virtex-II/Virtex-II Pro Instruction_Capture register:

- If the TAP is moved to the Pause-IR state as the Instruction_Capture bits are shifted out, the first bit that is clocked out of TDO after returning to Shift-IR will always be "1". The rest of the bits appear to be shifted out normally.

- If the Instruction_Capture register is read multiple times without resetting the TAP, the LSB appears to get stuck at "0".

These problems only exist in the Virtex-II/Virtex-II Pro architecture and have been resolved with the Virtex-4 and later device families.

Example from the 2v1000_fg456 BSDL File

attribute INSTRUCTION_CAPTURE of XC2V1000_FG456 : entity is

-- Bit 5 is 1 when DONE is released (part of startup sequence)

-- Bit 4 is 1 if house-cleaning is complete

-- Bit 3 is ISC_Enabled

-- Bit 2 is ISC_Done

"XXXX01";

Solution

You can use one of the following to work around this issue:

Method 1

Do not use the Pause-IR state when scanning the Instruction_Capture register. If a pause is required, TCK must be halted (often referred to as a "gated" TCK). See (Xilinx Answer 15983).

Method 2

You can modify the BSDL file as follows to prevent the scan tool from checking the status of the Instruction_Capture LSB:

attribute INSTRUCTION_CAPTURE of XC2V1000_FG456 : entity is

-- Bit 5 is 1 when DONE is released (part of startup sequence)

-- Bit 4 is 1 if house-cleaning is complete

-- Bit 3 is ISC_Enabled

-- Bit 2 is ISC_Done

"XXXX0X";

AR# 15403
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article