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AR# 15436

LogiCORE SPI-4.2 (POS-PHY L4) - Simulating the PL4 Core using dynamic alignment

Description

General Description:

How do I simulate the PL4 core using dynamic alignment?

Solution

This Answer Record applies to the PL4 Core only when dynamic alignment is used for simulation. Please read the following information carefully before simulating the PL4 core.

The design for the PL4 dynamic alignment solution requires that the timing simulation be performed in order to properly simulate the dynamic alignment per-bit de-skew capabilities of the Sink core. The dynamic alignment circuitry depends on the timing information available in the SDF file generated by NGDAnno tool after Placement and Routing. Therefore, you must do timing simulation to evaluate the performance of dynamic alignment.

The post-NGDBuild functional simulation model provided with the core is a Static Alignment simulation file, even though you have generated a Dynamic alignment core. This file is located in the CORE Generator project directory at:

<component_name>/test/<vhdl | verilog>/pl4_snk_top.<v | vhd>

This simulation model enables functional simulation of the entire core, with the exception of the dynamic alignment per-bit de-skew. This file is provided to evaluate the functionality of the core and to speed up simulation time.

This simulation model, while functionally equivalent, is not a cycle-true representation of the dynamic alignment PL4 core. The actual dynamic alignment core has additional latency that is not represented in this simulation model. If a cycle-true representation of the PL4 core is required for functional simulation, an additional 9 RDClk cycles of delay should be added in your design or testbench in front of the PL4 Sink Core (prior to RDat and RCtl inputs). However, if this cycle-true representation is not required for functional simulation, no change or modification is necessary to simulate the core.

After the design is run through Place And Route, complete timing simulation, including the dynamic alignment per-bit de-skew functionality, is possible through use of the SDF and Verilog or VHDL outputs from NGDAnno. Refer to the "Simulating the PL4 Core" section of the PL4 Design Example document for more information on setting up post-PAR simulations.

AR# 15436
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article