UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 15442

LogiCORE SPI-4.2 (POS-PHY L4) - PL4 Sink Core with dynamic alignment fails to activate PhaseAlignComplete, goes out of sync, or reports a DIP-4 error

Description

General Description:

When I use a SPI-4.2 (PL4) Sink Core with dynamic alignment, the following problems occur on my device:

1. The PL4 Sink Core (with dynamic alignment) fails to activate PhaseAlignComplete in response to a PhaseAlignRequest.

2. The PL4 Sink Core (with dynamic alignment) completes alignment as indicated by PhaseAlignComplete, but almost immediately loses synch (SnkOof becomes active) or indicates a large number of DIP-4 errors.

Solution

The dynamic alignment algorithm requires training patterns on the PL4 bus to complete the alignment. If PhaseAlignRequest is activated when the Sink logic is not receiving training patterns, the logic will fail to achieve lock.

Do not assert PhaseAlignRequest unless the Sink logic is indicating "out-of-frame" (SnkOof active). When the Sink State Machine is "out of frame," it will send "framing" patterns (all 11s) on its FIFO status channel. The SPI4.2 specification requires that the Source respond to this condition by sending continuous training patterns.

An alternative solution is to assert PhaseAlignRequest twice. The first request will fail, which causes the Sink logic to become "out-of-frame" (SnkOof indicated), and at this point, you can correctly assert PhaseAlignRequest. Note that there should be some lag (system-dependent) between the reception of the SnkOof indication and the assertion of the second PhaseAlignRequest to ensure that the Source side has actually started sending valid training sequences.

The testing of Dynamic Phase Alignment over a nominal range of temperature and voltage demonstrates that the Dynamic Phase Alignment solution has little or no sensitivity to device voltage or temperature variations. As a result, you do not need to realign the core unless the core is out of frame or a DIP4 error is indicated.

For additional information on SPI-4.2 (PL4) Dynamic Phase Alignment, please contact Xilinx Customer Support at:

http://support.xilinx.com/support/clearexpress/websupport.htm

AR# 15442
Date Created 09/03/2007
Last Updated 05/03/2010
Status Archive
Type General Article