AR# 15460: 5.1i SIMPRIMS - in a post-translate simulation, a glitch appears on the output of FDDRCPE
5.1i SIMPRIMS - in a post-translate simulation, a glitch appears on the output of FDDRCPE
Keywords: simulation, SIMPRIM, post, translate, glitch, FDDRCPE, DDR
General Description: When I run a post-translate simulation on a design that contains a FDDRCPE, a 100 ps glitch appears on the output. This glitch also appears when I run a post-MAP or post-PAR simulation without the SDF. Is the simulation correct?
The simulation behavior is not correct. The glitch is a result of the 100 ps default delay that is applied to each SIMPRIM component in the absence of an SDF file. The FDDRCPE is modeled by several SIMPRIM components, including two FFs and the MUXDDR. The MUXDDR switches between data inputs at the clock transition, but the new data is delayed 100 ps going through the FF. Therefore, the previous FF value is output from the MUXDDR for 100 ps.
The only current way to work around this issue is to run a post-MAP or post-PAR simulation with the SDF.
This problem will be fixed in the 6.1i software release.