In FPGA Editor, I modify a Virtex-II design so that it does not have a Phase Shift. Then, as required, I set the PSINCDEC, PSEN, and PSCLK pins to "0" by inverting, then connecting to a VCC pod.
However, the design does not pass DRC in BitGen, and reports the following error:
"ERROR:DesignRules:529 - Blockcheck: Illegal DCM connection. CLKOUT_PHASE_SHIFT is not configured VARIABLE for comp c_top_xilinx_block/i_demux_dcm, therefore all input phase shift pins (PSINCDEC, PSEN, and PSCLK) must be connected to GND."
Even though the design was set to FIXED or NONE, the PSDONE signal is still connected.
To work around this issue, check and remove the PSDONE connection.