General Description: Two BitGen problems can cause incorrect initialization values for the block RAM output registers in Virtex-II and Virtex-II Pro devices. (These problems exist in all versions of the 3.1i, 4.1i, and 4.2i software.)
Note that these problems DO NOT affect block RAM memory cells -- only the output registers are affected.
If the hexadecimal value "0xD" is specified as the initialization value for the block RAM output registers DOA[0-31] and DOB[0-31], BitGen will change this value to "0xF". The initialization values of the DOA[0-31] and DOB[0-31] output registers are specified by the INIT_A and INIT_B attributes.
This problem does not affect the block RAM memory cell initialization values, which are specified by the INIT_00 through INIT_3f values.
Issue 2: Corrupted SRVAL_A Value
The set/reset value that is specified for the output register on DOA28 will also be applied to DOA20; the value that is specified by the user for DOA20 will not be used. The output register set/reset value is specified by the SRVAL_A attribute. Note that this only affects block RAMs that are configured with port widths that use the DOA20 register.
Because these problems are caused by BitGen, the INIT_A, INIT_B and SRVAL_A values will appear to be correct in FPGA Editor. The problems will exist only in the .bit file.