We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 15546

5.1i XPower - A VCD file entry for BUFGCE does not propagate through to XPower


Keywords: XPower, BUFGCE, enable, output, frequency, clock, power

Urgency: Standard

General Description:
XPower automatically sets the output of a BUFGMUX to the same frequency as the buffer input, and as a result, the frequencies on the input and the output cannot differ.

Consequently, when I configure the BUFGMUX as a BUFGCE, the average output frequency is probably not the same as the average input frequency, and XPower sets an incorrect frequency.


This problem is caused by a bug in XPower. You can work around this issue as follows:

If the input clock net to the BUFGMUX (BUFGCE) has only one load (i.e., the BUFGMUX), manually set the input frequency to the average output frequency. For example, if the buffer is enabled half the time with an input frequency of 10 MHz, set the input to 5 MHz. If the input clock net has more than one load, you must take into consideration the impact of the power estimate on other parts of the circuit.

This problem was fixed in the 5.2i release.
AR# 15546
Date 11/03/2004
Status Archive
Type General Article
Page Bookmarked