When I simulate a PL4 Source core, glitches occur on the TDat and TCtl signals. This problem occurs on gate-level simulation as well as in timing simulation.
If you are targeting Virtex-II FPGA and using V.E. or an earlier core, this problem is caused by an issue with the modeling of DDR registers in the SimPrim model. There is a difference in the delay of positive and negative edges of the clock, which results in the glitches that occur on the TDat and TCtl signals.
This issue has been fixed in the ISE software 7.1i SimPrim models and you should not see any more glitches. If this is not the case, please open a WebCase at:
Skews on the TDat bus may often be mistaken for glitches. Since TDat is a 16-bit bus, there will be skew on these bits causing incorrect data to appear on the TDat bus. However, the incorrect data will be far enough from the clock edges and can be safely ignored.