- 133 MHz Virtex-II 2V1000-6 will be available in the PCI-X Lounge the week of November 11, 2002.
- The 5.1i software with Service Pack 2 will be supported.
- Customers who purchase the PCI-X 64/100 core DO-DI-PCIX64-VE core will have free access to the 133 MHz version with no upgrade charge.
- APD is creating a PCI-X I/O Standard for Virtex-II Pro, and support is tentatively scheduled to be included in the software by March, 2003. After the I/O standard is verified, we will verify whether the PCI-X core meets timing and will then determine when a Virtex-II Pro product will be released. (The 2VP7FF672-7 is currently being targeted.)
V3.0 PCI 64/66, 32/33
- 5.1i support has been delayed due to bugs that were introduced in the Xilinx tools, but all problems will be fixed in 5.1i Service Pack 3. We plan to release the PCI core for 5.1i Service Pack 3 in mid-December, 2002 to coincide with the SP3 release.
The PCI Express core was developed using the 5.1i software and should be fully 5.1i-compatible
- Rapid I/O version 1.0
Rapid I/O version 1.0 is not fully qualified with the 5.1i software. Rapid I/O users should use the 4.2i software until the release of a new 5.1i- compatible version in late October, 2002.
CORE Generator Basic Element Cores
- RAM-based Shift Register v6.0
The RAM-based Shift Register v6.0 cannot be mapped using the 5.1i software. Please see (Xilinx Answer 15551) for more details.
You must use 5.1i-compatible versions of evaluation and release cores for licensed DSP Forward Error Correction (FEC) cores (Reed Solomon, Viterbi Decoder, and Interleaver/De-interleaver). ISE 5.1i versions of our FEC cores are available on the Xilinx web site as of August 26, 2002. (This includes both the evaluation and complete versions of these cores.)
These cores have the same features as those released for ISE 4.2i -- they have simply been ported and verified for the 5.1i software. Users of these cores must download and install the latest version after the 5.1i software is installed. If the appropriate versions of these cores are not installed, only the "info" versions of the cores will be visible in CORE Generator.
Please also note that the 4.1i and 4.2i archives are not compatible with 5.1i and should not be installed over the 5.1i software.
- POS PHY Level 4 (PL4) v5.0
The recently released 5.0 version of the PL4 core has been developed to work with Xilinx 4.2i software only. Please see (Xilinx Answer 15555) for more information.
- POS-PHY Level 3 (PL3) v3.0 Link Layer Interface Cores: Fully qualified with 5.1i
- POS PHY Level 3 (PL3) v2.01 Link Layer Interface Cores: Fully qualified with 5.1i
- POS-PHY Level 3 (PL3) v1.0 Link Layer Interface Cores: Not qualified with 5.1i
- POS-PHY Level 3 (PL3) v1.0 Physical Layer Interface Cores: Not qualified with 5.1i
- Flexbus4 v1.0 (Single channel, 4-channel): Fully qualified with 5.1i
- Gigabit Ethernet MAC with PCS/PMA v2.0, v2.1
- 10 Gigabit Ethernet MAC with XAUI v2.0, v2.1
The above two core configurations will not work in the 5.1i software due to changes in the port maps of the MGTs associated with BREFCLK in the 5.1i Xilinx UniSim library. If you must use one of these cores with the 5.1i software, please contact Xilinx Customer Support to request a special build of these cores. (Please see (Xilinx Answer 15533) for more details.)
System Generator for PowerPC and MicroBlaze
System Generator for DSP
The 5.1i-compatible versions of the evaluation and release cores must be used for the licensed DSP Forward Error Correction (FEC) cores (Reed Solomon, Viterbi Decoder, and Interleaver/De-interleaver) as noted above under the "DSP Cores" heading.