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AR# 15665

5.1i XST - The implementation of a shift register model does not produce the expected results

Description

Keywords: ISE, 5.1i, XST, shift, register, synthesis, implementation, simulation, result

Urgency: Standard.

General Description:
When I implement a shift register and use the following statement in my code, the expected results are not produced in post-synthesis simulation:

process (CLK, RST, START)
begin

if rising_edge(CLK) then
if RST='1' then

control_int <= (others=>'0');

else
if START='1' then

control_int <= (0=>'1', others=>'0');

else

control_int <= control_int(width-2 downto 0) & '0';

end if;
end if;
end if;

end process;

CONTROL <= control_int;

XST does not report any warnings or error messages regarding the code architecture. What could be wrong?

Solution

XST is not implementing the following syntax correctly:

control_int <= (0=>'1', others=>'0');

To work around this problem, use the following statement:

process (CLK, RST, START)
begin

if rising_edge(CLK) then
if RST='1' then

control_int <= (others=>'0');

else
if START='1' then

control_int(0) <= '1';
control_int(width-1 downto 1) <= (others=>'0');

else

control_int <= control_int(width-2 downto 0) & '0';

end if;
end if;
end if;

end process;

CONTROL <= control_int;
AR# 15665
Date Created 09/23/2002
Last Updated 10/20/2005
Status Archive
Type General Article