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AR# 15673

LogiCORE SPI-4.2 (POS-PHY L4) v5.2 - PAR error: "Place:1897 - A global clock component <pl4_src_top0/pl4_src_clk0/tsclk_bufg0> configured as a selectable mux is placed in site BUFGMUX3S..."


General Description:

When I attempt to place a BUFGMUX or a BUFG in a certain location, the following error is reported in PAR:

"ERROR:Place:1897 - A global clock component <pl4_src_top0/pl4_src_clk0/tsclk_bufg0> configured as a selectable mux is placed in site BUFGMUX3S. This configuration requires that the global clock site BUFGMUX2P either be empty or contain a global buffer or mux with the inputs IN0 and IN1 either not drive by a signal or driven by the same signals as the original mixes IN1 and IN0 pins respectively in order to route up both of the inputs.

In other words, the input signal for IN0 on one buffer must be the same as the input signal driving IN1 on the other buffer (or one of them must not be driven) to place the two buffers in the paired sites.

The site BUFGMUX2P has the global buffer <pl4_src_top0/pl4_src_clk0/td clk0_bufg0> placed there. This design is unroutable. Please correct this problem before continuing."


This issue has been fixed in v6.0 of the SPI4.2 core.

The PL4 source core uses one BUFGMUX "pl4_src_clk0/tsclk_bufg0". Because of Virtex-II device limitations, the adjacent BUFGMUX cannot be used, even as a BUFG. An attempt to use it causes the PAR error above.

Xilinx is aware that not using the adjacent BUFGMUX is wasting a resource, and this issue will be addressed in a future version of the PL4 core.

AR# 15673
Date 05/03/2010
Status Archive
Type General Article