We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 15698

6.1i PAR - When I use back-annotated pin locations, an error is reported: "ERROR:Place:44 - The global clocks xxa(BUFGMUX1P) and xxb(BUFGMUX1S) ...impossible to route"


Keywords: PAR, back-annotated, pin, locations, primary, secondary, pair, 5.1i

Urgency: Standard

General Description:
Without pin locking, my implementation containing DCMs completes successfully. However, when I attempt to lock the pins to the same locations using the "Back-annotate Pin Locations" utility, the clock placer incorrectly places the DCMs, and the following error is reported in PAR:

"ERROR:Place:44 - The global clocks ireq2_ibufg/BUFG (BUFGMUX1P) and egr1_ibufg/BUFG (BUFGMUX1S) are locked into a primary / secondary site pair. It is impossible to route all of the clock loads for both of these clocks using the global clock routing resource. Only one of primary/secondary pair clocks have access to any one quadrant via global (high drive/low delay/low skew) routing resources. If these two clocks drive clock inputs in the same quadrant the nets will not be routable using the global clock routing resources."


This issue was fixed in the 6.1i software.

You can also work around this issue by locking the DCMs to the appropriate location.


For clock routing rules and restrictions see the Virtex-II Hardware User Guide, Chapter 2, "Using Global Clock Networks" at:
AR# 15698
Date 10/20/2008
Status Archive
Type General Article