UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 15712

5.1i XST - An incorrect subtractor is inferred for results larger than 32 bits

Description

Keywords: XST, Verilog, subtract, 32, bit

Urgency: Standard

General Description:
Carry logic "cn" is incorrectly synthesized with the following Verilog design:

module top (a, b, cn, res);
input [31:0] a, b;
output [31:0] res;
output cn;

assign {cn, res} = a - b;
endmodule

Solution

This problem is fixed in the latest 5.1i Service Pack available at:
http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 5.1i Service Pack 2.

The only other way to work around this issue is to keep your subtractors under 32 bits.
AR# 15712
Date Created 09/27/2002
Last Updated 10/20/2005
Status Archive
Type General Article