UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 15732

5.1i HDL Bencher - Testbenches created by HDL Bencher for multiple clock designs do not toggle the input signals associated with the faster clocks or asynchronous signals

Description

Keywords: testbench, multiple, clocks, toggle, asynchronous, period, stops, frequency, Bencher, test fixture

Urgency: Standard

General Description:
If the "multiple clocks" option is used in HDL Bencher, a faulty testbench may be created. This will occur if one clock is faster than another, or if asynchronous signals are used. The symptom of this problem is that inputs associated with the faster clock and/or the asynchronous signals will stop toggling or not toggle at all.

If you view the testbench file (*.tfw for Verilog flow or *.thw for VHDL flow), you will see the proper time intervals or WAIT times. However, transition statements will be missing, as illustrated in the following example:

BEGIN
-- --------------------
din <= transport '1';
-- --------------------
WAIT FOR 20 ns; -- Time=20 ns
din <= transport '0';
-- --------------------
WAIT FOR 20 ns; -- Time=40 ns
din <= transport '1';
-- --------------------
WAIT FOR 10 ns; -- Time=50 ns
din <= transport '0';
-- --------------------
WAIT FOR 30 ns; -- Time=80 ns
din <= transport '1';
-- --------------------
WAIT FOR 20 ns; -- Time=100 ns
din <= transport '0';
-- --------------------
WAIT FOR 20 ns; -- Time=120 ns
-- --------------------
WAIT FOR 20 ns; -- Time=140 ns
-- --------------------
WAIT FOR 20 ns; -- Time=160 ns
-- --------------------
WAIT FOR 41 ns; -- Time=201 ns
-- --------------------

Solution

This problem is fixed in the latest 5.1i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 5.1i Service Pack 2.

You may also work around this problem by moving the end of the testbench far beyond the original time being tested. To do this, either drag the blue "end of testbench" line to the desired time, or scroll to the desired time, right-click, and select "Set end of testbench".
AR# 15732
Date Created 10/01/2002
Last Updated 02/07/2006
Status Archive
Type General Article