When I implement a design in which the clock divider output is connected to an I/O pin, an error message similar to the following is reported:
"FATAL_ERROR:Portability:PortDynamicLib.c:278:1.16 - dll open of library <C:/Xilinx/epld/bin/nt/libCpld_Ngd2nds.dll> failed due to an unknown reason.
Process will terminate."
This error is reported because there is an illegal connection in the design. Clock divider outputs may only be connected to the clock ports of registers; they may not connect to combinatorial logic or output pins.
This is corrected in ISE version 6.1i.