General Description: When I perform a timing simulation on a Virtex or Virtex-E design, problems with the local reset occur because a large delay was incorrectly annotated to the reset line.
In the timing simulation netlist, the local reset and GSR are "ORed" together. The net delays for the local reset and GSR are annotated to the input ports of the OR gate.
For example: (CELL (CELLTYPE "X_OR2") (INSTANCE data_reg2_FFY_RSTOR) (DELAY (ABSOLUTE (PORT I0 (579:579:579)(579:579:579)) (PORT I1 (6955:6955:6955)(6955:6955:6955)) (IOPATH I0 O (0:0:0)(0:0:0)) (IOPATH I1 O (0:0:0)(0:0:0)) ) ) )
The output of the OR gate goes to the registers in the design that are reset or set by this local reset. As the net delays for the reset lines have already been annotated to the OR gate, there should not be any delay on the PORT SET or PORT RST of the registers. In some cases, the net delay for GSR was incorrectly annotated to the these ports, as illustrated below:
(CELL (CELLTYPE "X_FF") (INSTANCE data_reg2_7) (DELAY (ABSOLUTE (PORT I (1354:1354:1354)(1354:1354:1354)) (PORT CLK (364:364:364)(364:364:364)) (PORT SET (6955:6955:6955)(6955:6955:6955)) (PORT RST (6955:6955:6955)(6955:6955:6955)) (IOPATH CLK O (738:738:738)(738:738:738)) (IOPATH SET O (576:576:576)(576:576:576)) (IOPATH RST O (576:576:576)(576:576:576)) ) )
In the example above, the local reset and GSR are delayed by an extra 7ns. This is not the correct behavior.