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AR# 15779

Synplify - How do I infer input dual data rate (DDR) registers?


General Description:

How do I infer dual data rate (DDR) registers?


Synplify infers regular FDs (Xilinx flip-flop primitives) with the following code. Since the FF's clock is the inverse of the other clock, the implementation tools can pack both input registers into the same IOB to create dual data rate (DDR) registers.

Input DDR VHDL Example

library ieee;

use ieee.std_logic_1164.all;

entity input_ddr is

Port ( d : in std_logic;

clk : in std_logic;

q_and : out std_logic);

end input_ddr;

architecture input_ddr_arch of input_ddr is

signal q1, q2 : std_logic;


process (clk) begin

if clk'event and clk = '1' then

q1 <= d;

end if;

end process;

process (clk) begin

if clk'event and clk = '0' then

q2 <= d;

end if;

end process;

q_and <= q1 and q2;

end input_ddr_arch;

Input DDR Verilog Example

module input_ddr(d,clk,q_and);

input d;

input clk;

output q_and;

reg q1, q2;

always @(posedge clk) q1 <= d;

always @(negedge clk) q2 <= d;

assign q_and = q1 & q2;


Output DDRs cannot currently be inferred. For OFDDRx instantiation templates, please refer to the Libraries Guide at:


AR# 15779
Date 12/15/2012
Status Active
Type General Article